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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 123 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? non-volatile program and data memories ? 2/4/8k byte of in-system prog rammable program memory flash (attiny261/461/861) endurance: 10,000 write/erase cycles ? 128/256/512 by tes in-system prog rammable eeprom (a ttiny261/461/861) endurance: 100,000 write/erase cycles ? 128/256/512 bytes internal sram (attiny261/461/861) ? programming lock for self-program ming flash program and eeprom data security ? peripheral features ? 8/16-bit timer/coun ter with prescaler and two pwm channels ? 8/10-bit high speed timer/counter with separate prescaler 3 high frequency pwm outputs with separate output compare registers programmable dead time generator ? universal serial interface with start condition detector ? 10-bit adc 11 single ended channels 16 differential adc channel pairs 15 differential adc channel pairs with programmable gain (1x, 8x, 20x, 32x) ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? external and internal interrupt sources ? low power idle, adc noise reduction, and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal calibrated oscillator ? i/o and packages ? 16 programmable i/o lines ? 20-pin pdip, 20-pin soic and 32-pad mlf ? operating voltage: ? 1.8 - 5.5v for attiny261v/461v/861v ? 2.7 - 5.5v for attiny261/461/861 ? speed grade: ? attiny261v/461v/861v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 10 mhz @ 2.7 - 5.5v ? attiny261/461/861: 0 - 10 mhz @ 2.7 - 5.5v, 0 - 20 mhz @ 4.5 - 5.5v ? industrial temperature range ? low power consumption ? active mode: 1 mhz, 1.8v: 380 a ? power-down mode: 0.1 a at 1.8v 8-bit microcontroller with 2/4/8k bytes in-system programmable flash attiny261/v attiny461/v attiny861/v preliminary summary 2588bs?avr?11/06
2 2588bs?avr?11/06 attiny261/461/861 1. pin configurations figure 1-1. pinout attiny261/461/861 note: the large center pad underneath the qf n/mlf package should be soldered to ground on the board to ensure good mechanical stability. 1.1 disclaimer typical values contained in this data s heet are based on simulations and characte rization of other avr microcontrollers manufactured on the same process technol ogy. min and max values will be availa ble after the device is characterized. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (mosi/di/sda/oc1a/pcint8) pb0 (miso/do/oc1a/pcint9) pb1 (sck/usck/scl/oc1b/pcint10) pb2 (oc1b/pcint11) pb3 vcc gnd (adc7/oc1d/clki/xtal1/pcint12) pb4 (adc8/oc1d/clko/xtal2/pcint13) pb5 (adc9/int0/t0/pcint14) pb6 (adc10/reset/pcint15) pb7 pa0 (adc0/di/sda/pcint0) pa1 (adc1/do/pcint1) pa2 (adc2/int1/usck/scl/pcint2) pa3 (aref/pcint3) agnd avcc pa4 (adc3/icp0/pcint4) pa5 (adc4/ain2/pcint5) pa6 (adc5/ain0/pcint6) pa7 (adc6/ain1/pcint7) pdip/soic 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 nc (oc1b/pcint11) pb3 nc vcc gnd nc (adc7/oc1d/clki/xtal1/pcint12) pb4 (adc8/oc1d/clko/xtal2/pcint13) pb5 nc pa2 (adc2/int1/usck/scl/pcint2) pa3 (aref/pcint3) agnd nc nc avcc pa4 (adc3/icp0/pcint4) nc (adc9/int0/t0/pcint14) pb6 (adc10/reset/pcint15) pb7 nc (adc6/ain1/pcint7) pa7 (adc5/ain0/pcint6) pa6 (adc4/ain2/pcint5) pa5 nc pb2 (sck/usck/scl/oc1b/pcint10) pb1 (miso/do/oc1a/pcint9) pb0 (mosi/di/sda/oc1a/pcint8) nc nc nc pa0 (adc0/di/sda/pcint0) pa1 (adc1/do/pcint1) qfn/mlf
3 2588bs?avr?11/06 attiny261/461/861 2. overview the attiny261/461/861 is a low-power cmos 8-bi t microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the attiny261/461/861 achieves throughputs ap proaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. 2.1 block diagram figure 2-1. block diagram port a (8) port b (8) usi timer/counter1 timer/counter0 a/d conv. internal bandgap analog comp. sram flash eeprom watchdog oscillator watchdog timer oscillator circuits / clock generation power supervision por / bod & reset vcc gnd program logic debugwire agnd aref avcc data b u s pa[0..7] pb[0..7] 11 reset xtal[1..2] cpu 3
4 2588bs?avr?11/06 attiny261/461/861 the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the attiny261/461/861 provides the following feat ures: 2/4/8k byte of in-system programmable flash, 128/256/512 bytes eeprom, 128/256/512 bytes sram, 6 general purpose i/o lines, 32 general purpose working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed timer/counter, universal serial interface, internal and external interrupts, a 4-channel, 10-bit adc, a programmable watc hdog timer with in ternal oscillato r, and three so ftware select- able power saving modes. the idle mode stops the cpu while allowing the sram, timer/counter, adc, analog comparator, and interrupt system to continue functioning. the power-down mode saves the register contents, di sabling all chip functions until the next inter- rupt or hardware reset. the adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switch ing noise during adc conversions. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be re-programmed in-system through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core. the attiny261/461/861 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emu- lators, and evaluation kits. 2.2 pin descriptions 2.2.1 vcc supply voltage. 2.2.2 gnd ground. 2.2.3 avcc analog supply voltage. 2.2.4 agnd analog ground. 2.2.5 port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the attiny261/461/861 as listed on page 65 .
5 2588bs?avr?11/06 attiny261/461/861 2.2.6 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the attiny261/461/861 as listed on page 61 . 2.2.7 r eset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 23-3 on page 189 . shorter pulses are not guaranteed to generate a reset.
6 2588bs?avr?11/06 attiny261/461/861 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr.
7 2588bs?avr?11/06 attiny261/461/861 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c page 9 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 page 12 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 12 0x3c (0x5c) reserved ? 0x3b (0x5b) gimsk int1 int0 pcie1 pcie0 ? ? ? ? page 51 0x3a (0x5a) gifr intf1 intf0 pcif ? ? ? ? ? page 51 0x39 (0x59) timsk ocie1d ocie1a ocie1b ocie0a ocie0b toie1 toie0 ticie0 page 86 , page 123 0x38 (0x58) tifr ocf1d ocf1a oc f1b ocf0a ocf0b tov1 tov0 icf0 page 87 , page 124 0x37 (0x57) spmcsr ? ? ? ctpb rflb pgwrt pgers spmen page 166 0x36 (0x56) prr prtim1 prtim0 prusi pradc page 35 0x35 (0x55) mcucr ?pudsesm1sm0 ?isc01isc00 page 37 , page 68 , page 50 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf page 44 , 0x33 (0x53) tccr0b ? ? ? tsm psr0 cs02 cs01 cs00 page 70 0x32 (0x52) tcnt0l timer/counter0 counter register low byte page 85 0x31 (0x51) osccal oscillat or calibration register page 32 0x30 (0x50) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm1a pwm1b page 113 0x2f (0x4f) tccr1b pwm1x psr1 dtps11 dtps10 cs13 cs12 cs11 cs10 page 166 0x2e (0x4e) tcnt1 timer/counter1 counter register page 121 0x2d (0x4d) ocr1a timer/counter1 output compare register a page 121 0x2c (0x4c) ocr1b timer/counter1 output compare register b page 122 0x2b (0x4b) ocr1c timer/counter1 output compare register c page 122 0x2a (0x4a) ocr1d timer/counter1 output compare register d page 123 0x29 (0x49) pllcsr lsm pcke plle plock page 89 0x28 (0x48) clkpr clkpce clkps3 clkps2 clkps1 clkps0 page 32 0x27 (0x47) tccr1c com1a1s com1a0s co m1b1s com1b0s com1d1 com1d0 foc1d pwm1d page 117 0x26 (0x46) tccr1d fpie1 fpen1 fpnc1 fpes1 fpac1 fpf1 wgm11 wgm10 page 119 0x25 (0x45) tc1h tc19 tc18 page 121 0x24 (0x44) dt1 dt1h3 dt1h2 dt1h1 dt1h0 dt1l3 dt1l2 dt1l1 dt1l0 page 124 0x23 (0x43) pcmsk0 pcint7 pcint6 pcin t5 pcint4 pcint3 pcint2 pcint1 pcint0 page 52 0x22 (0x42) pcmsk1 pcint15 pcint14 pcin t13 pcint12 pcint11 pcint10 pcint9 pcint8 page 52 0x21 (0x41) wdtcr wdif wdi e wdp3 wdce wde wdp2 wdp1 wdp0 page 44 0x20 (0x40) dwdr dwdr[7:0] page 35 0x1f (0x3f) eearh eear8 page 21 0x1e (0x3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 21 0x1d (0x3d) eedr eeprom data register page 22 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere page 22 0x1b (0x3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 68 0x1a (0x3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 68 0x19 (0x39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 68 0x18 (0x38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 68 0x17 (0x37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 68 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 68 0x15 (0x35) tccr0a tcw0 icen0 icnc0 ices0 acic0 wgm00 page 84 0x14 (0x34) tcnt0h timer/counter0 counter register high byte page 85 0x13 (0x33) ocr0a timer/counter0 output compare register a page 85 0x12 (0x32) ocr0b timer/counter0 output compare register b page 85 0x11 (0x31) usipp usipos page 137 0x10 (0x30) usibr usi buffer register page 134 0x0f (0x2f) usidr usi data register page 133 0x0e (0x2e) usisr usisif usioif usipf u sidc usicnt3 usicnt2 usicnt1 usicnt0 page 134 0x0d (0x2d) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc page 135 0x0c (0x2c) gpior2 general purpose i/o register 2 page 23 0x0b (0x2b) gpior1 general purpose i/o register 1 page 23 0x0a (0x2a) gpior0 general purpose i/o register 0 page 23 0x09 (0x29) acsrb hsel hlev acm2 acm1 acm0 page 141 0x08 (0x28) acsra acd acbg aco aci acie acme acis1 acis0 page 138 0x07 (0x27) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 154 0x06 (0x26) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 157 0x05 (0x25) adch adc data register high byte page 158 0x04 (0x24) adcl adc data register low byte page 158 0x03 (0x23) adcsrb bin gsel refs2mux5adts2adts1adts0 page 158 0x02 (0x22) didr1 adc1 0d adc9d adc8d adc7d page 160 0x01 (0x21) didr0 adc6d adc5d adc 4d adc3d arefd adc2d adc1d adc0d page 160 0x00 (0x20) tccr1e ? - oc1oe5 oc1oe4 oc1oe3 oc1oe2 oc1oe1 oc1oe0 page 120
8 2588bs?avr?11/06 attiny261/461/861 note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specified bit, and can theref ore be used on registers contai ning such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only.
9 2588bs?avr?11/06 attiny261/461/861 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
10 2588bs?avr?11/06 attiny261/461/861 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
11 2588bs?avr?11/06 attiny261/461/861 6. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc ,see figure 23.3 on page 187 6.1 attiny261 speed (mhz) (3) power supply ordering code (2) package (1) operational range 10 1.8 - 5.5v attiny261v-10mu ATTINY261V-10PU attiny261v-10su 32m1-a 20p3 20s2 industrial (-40 c to 85 c) 20 2.7 - 5.5v attiny261-20mu attiny261-20pu attiny261-20su 32m1-a 20p3 20s2 industrial (-40 c to 85 c) package type 32m1-a 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s2 20-lead, 0.300" wide, plastic gull wing small outline package (soic)
12 2588bs?avr?11/06 attiny261/461/861 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc ,see figure 23.3 on page 187 6.2 attiny461 speed (mhz) (3) power supply ordering code (2) package (1) operational range 10 1.8 - 5.5v attiny461v-10mu attiny461v-10pu attiny461v-10su 32m1-a 20p3 20s2 industrial (-40 c to 85 c) 20 2.7 - 5.5v attiny461-20mu attiny461-20pu attiny461-20su 32m1-a 20p3 20s2 industrial (-40 c to 85 c) package type 32m1-a 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s2 20-lead, 0.300" wide, plastic gull wing small outline package (soic)
13 2588bs?avr?11/06 attiny261/461/861 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc ,see figure 23.3 on page 187 6.3 attiny861 speed (mhz) (3) power supply ordering code (2) package (1) operational range 10 1.8 - 5.5v attiny861v-10mu attiny861v-10pu attiny861v-10su 32m1-a 20p3 20s2 industrial (-40 c to 85 c) 20 2.7 - 5.5v attiny861-20mu attiny861-20pu attiny861-20su 32m1-a 20p3 20s2 industrial (-40 c to 85 c) package type 32m1-a 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s2 20-lead, 0.300" wide, plastic gull wing small outline package (soic)
14 2588bs?avr?11/06 attiny261/461/861 7. packaging information 7.1 32m1-a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32m1-a , 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, d 32m1-a 8/19/04 3.10 mm exposed pad, micro lead frame package (mlf) common dimensions (unit of measure = mm) symbol min nom max note d1 d e1 e e b a3 a2 a1 a d2 e2 0.08 c l 1 2 3 p p 0 1 2 3 a 0.80 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d 5.00 bsc d1 4.75 bsc d2 2.95 3.10 3.25 e 5.00 bsc e1 4.75bsc e2 2.95 3.10 3.25 e 0.50 bsc l 0.30 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec standard mo-220, fig. 2 (anvil singulation), vhhd-2. top view side view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k
15 2588bs?avr?11/06 attiny261/461/861 7.2 20p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20p3 , 20-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) c 20p3 1/12/04 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 25.493 ? 25.984 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation ad. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
16 2588bs?avr?11/06 attiny261/461/861 7.3 20s2
17 2588bs?avr?11/06 attiny261/461/861 8. errata 8.1 errata attiny261 the revision letter in this section refe rs to the revision of the attiny261 device. 8.1.1 rev a no known errata. 8.2 errata attiny461 the revision letter in this section refe rs to the revision of the attiny461 device. 8.2.1 rev b yield improvement. no known errata. 8.2.2 rev a no known errata. 8.3 errata attiny861 the revision letter in this section refe rs to the revision of the attiny861 device. 8.3.1 rev b no known errata. 8.3.2 rev a not sampled.
18 2588bs?avr?11/06 attiny261/461/861 9. datasheet revision history 9.1 rev. 2588a ? 11/06 9.2 rev. 2588a ? 10/06 1. updated ?ordering information? on page 222 . 2. updated ?packaging information? on page 225 . 1. initial revision.
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